Introduction

In this blog article, we will take a look at three different EtherCAT Master software stacks. For each option and approach, we will look at the advantages and disadvantages, the main differences between them, and also the expected costs. Included in this comparison is the proprietary solution from acontis technologies the EC-Master and two open source implementations. The two open source implementations included in the article are the IgH EtherCAT-Master® as part of the EtherLab® distributed by IgH and the Simple Open EtherCAT Master (SOEM) mainly driven by rt-labs. All three stacks are available as source code and can be compiled for different operating systems and processor architectures. Some with more effort, some with less. But let’s see what we will get…

Paper work

The best specification for an EtherCAT Master SW stack in the early days around 2004 and 2005 was the EtherCAT Master Sample Code (MSC), as the EtherCAT Communication Specification Version 1.0 was missing precise master stack definitions. Still today, the succeeding ETG.1000 EtherCAT Specification and other documents lack these precise master stack definitions. To get more information about the master stack almost everybody had/has to kind of re-engineer the MSC to understand the state machines, algorithms and protocols that are required to operate an EtherCAT network.

acontis EC-Master

acontis technologies GmbH was founded in 2001 and has been a member of the EtherCAT Technology Group (ETG) since 2004 and therefore one of the earliest members of the ETG. acontis started the development of their own EtherCAT Master software (eventually named EC-Master) on the basis of the MSC from Beckhoff as that was and is only available for the Windows operating system (OS). acontis added a lot of error-handling routines as error handling was a big missing part of the MSC. MSC also did not have the purpose to capture every error case. Over time, development of Cable Redundancy, Hot Connect and Master Redundancy, and many other useful features have also been added.

After 20 years of development, EC-Master has been ported to numerous operating systems, processor architectures and Ethernet controllers. Along the way acontis has reached profound knowledge in the EtherCAT technology and in real-time applications. Customers of EC-Master have expressed that they value the responsiveness and knowledge of acontis team when it comes to troubleshooting, support, and finding new solutions to challenging problems.

Architecture

EC-Master is mainly written in C++, but there are Application Programming Interfaces (APIs) for C/C++, C# and Python. The stack has almost no dependencies on any 3rd party libraries and has just two very thin interfaces to the operating system and the Ethernet controller. These abstraction layers are what makes it easy to implement support for new operating systems, processor architectures or network adapters.

Figure 1 EC-Master architecture

Who is maintaining the software?

The product is mostly maintained by the employees and team members of the acontis technologies, but also their over 500 customers worldwide contribute to the improvement of the source code by filing bugs, issues, and proposing solutions to certain problems.

License Terms

There are mainly two different licensing types: The software can be purchased as a library or as source code. The license is tied to a specific project, operating system and processor architecture. Normally a customer will start with a fully featured evaluation package and then buy the Software Development Kit (SDK). After the customer has developed their product and they transition to marketing and selling it, runtime licenses are available for purchase, and an optional maintenance subscription is available to get extended support and product updates.

IgH EtherCAT Master® (EtherLab®)

The IgH Gesellschaft für Ingenieurleistungen mbH was founded in 1995 and has its roots in hydraulics. Over the years they continued their work in a lot of different special mechanical and electromechanical projects. Also, the IgH is listed as an ETG member in a press release from March 2004. The first release of the IgH EtherCAT Master® as part of the EtherLab® package dates back to August 2006 and already addressed CAN application protocol over EtherCAT services (CoE) and Ethernet tunneled over EtherCAT services (EoE) with the help of mailboxes. The last tarball was released with 1.5.2 in 2013 since then the version was not bumped for the benefit of a continues delivery.

Architecture

Luckily, there is substantial documentation for the IgH EtherCAT Master®. Also, there is a description of the architecture. The IgH EtherCAT Master® is implemented as a Linux Kernel Space module and supports Linux real-time extensions like Preempt RT. Network adapters are abstracted by device modules. The IgH EtherCAT Master® is tied to the Linux operating system and written in C.

Figure 2 IgH EtherCAT Master® architecture

One special behavior of this EtherCAT master stack we have encountered is that the acyclic data is packed into cyclic frames. This has some effect on the cycle time the certain slaves encounter especially when the time is taken on full reception of the frame.

Who is maintaining the software?

Florian Pose from the IgH is responsible for almost all of the changes (>90%) in this stack since it was releases the first time. Florian's work effort and perseverance are admirable, and all while not undermining the commits of the other contributors.

License Terms

The entire source code available from IgH is licensed under the GNU General Public License version 2 (GPLv2). So consideration should be made that a user of this software may have to also distribute the source code of any derived works.

Simple Open EtherCAT Master (SOEM)

The Flanders Mechatronics Technology Centre (FMTC) decided to make its EtherCAT master implementation (formerly known as EtherCAT master library (EML)) publicly available in 2006. According to certain pages on the Internet, SOEM has its roots in this EtherCAT master library from FMTC. It was written for and tested on eCos operating system. Some of the source files also name Arthur Ketels of the Speciaal Machinefabriek Ketels v.o.f. as the author. Also, the TU/e Technische Universiteit Eindhoven is stated in the license file.

Architecture

SOEM is written in C, and out of the box it runs as a user space application. OS and Ethernet adapters are abstracted by two interfaces. These interfaces depend on the OS and the network adapter interface and can be implemented with around 700-1000 lines of code. Adaptions to a number of different operating systems and network adapters are available (see also Supported Operating Systems, CPU architectures and Ethernet interfaces).

Figure 3 SOEM architecture

Who is maintaining the software?

This implementation seems to be supported and maintained mainly by employees of rt-labs and Arthur Ketels. The last official release dates back to July 2019 (v1.4.0).

License Terms

Similarly to the IgH EtherCAT Master®, SOEM is also licensed under GPLv2, but with a special exception that it is allowed to compile it with further application code without being required to share this derived work with the open source community. rt-labs also offers a paid commercial license per product/project. It is not clear what the difference is between the freely available and commercial version, although it appears to be that some support and maintenance is included with the paid commercial license.

Supported Operating Systems, CPU architectures and Ethernet interfaces

In the following table we compare which operating system, CPU architecture and Ethernet interface combinations are supported by these EtherCAT software stacks. Among the operating systems there are real-time operating systems (RTOS) and non-RTOS. CPU architectures include 32 and 64-bit, along with big and little-endian.

As all three stacks are available in source code, it is possible in principle to adapt to every OS, architecture and network hardware with more or less effort. Therefore, we will just focus on what is currently available out of the box. Since acontis is offering this information already and we do this comparison for our customers and potential we only guarantee the statements for the EC-Master. Furthermore since we were not able to compile every stack for every OS, architecture and network adapter, we rely in what is stated in the documentation and what we see in the source code.

x full support
x1 someone used or tried to use it in a project/some projects
x2 as 32 bit application on 64 bit Windows
x3 there is code existent

Table 1 Supported OSs, CPU architectures and network adapters

EC-Master supports more than 147 different combinations of processor architectures, OS and network adapters. IgH EtherCAT Master® 21 and SOEM 7. 34 solutions for Linux exist (26 by the EC-Master and 8 Open Source). Of importance to note is the number of combinations that is available for EC-Master and the list is still incomplete. A full list can be found on the manuals page to the stack. Also of note, SOEM is the only stack that supports Erika Enterprise RTOS, a royalty-free automotive OSEK/VDX certified hard RTOS.

Supported EtherCAT Master Features

As we highlighted the supported OS, architectures, and Ethernet adapters, let’s also review the supported features according to the EtherCAT Master Classes ETG.1500 document for a Master Class A. Important features include the possibility to import EtherCAT Network Information files (ENI) (EtherCAT XML Master Configuration), documentation, error handling and support.

Feature name

Short description

ETG.1500

EC-Master

SOEM

IgH EtherCAT Master®

Basic Features

Service Commands

Support of all commands

shall if ENI import support

2

IRQ field in datagram

Use IRQ information from Slave in datagram header

should

Slaves with Device Emulation

Support Slaves with and without application controller

shall

EtherCAT State Machine

Support of ESM special behavior

shall

Error Handling

Checking of network or slave errors, e.g. Working Counter

shall

3

3

VLAN

Support VLAN Tagging

may

EtherCAT Frame Types

Support EtherCAT Frames

shall

UDP Frame Types

Support UDP Frames

may

Process Data Exchange

Cyclic PDO

Cyclic process data exchange

shall

Multiple Tasks

Different cycle tasks

Multiple update rates for PDO

may

1

Frame repetition

Send cyclic frames multiple times to increase immunity

may

Network Configuration

Online scanning

Network configuration functionality included in EtherCAT Master

at least one

of them

Reading ENI

Network Configuration taken from ENI file

at least one

of them

Compare Network configuration

Compare configured and existing network configuration during boot-up

shall

Explicit Device identification

Identification used for Hot Connect and prevention against cable swapping

should

Station Alias Addressing

Support configured station alias in slave,

i.e. enable 2nd Address and use it

may

Access to EEPROM

Support routines to access EEPROM via ESC register

read shall

write may

Mailbox Support

Support Mailbox

Main functionality for mailbox transfer

shall

3

Mailbox Resilient Layer

Support underlying resilient layer

shall

Multiple Mailbox channels

 

may

Mailbox polling

Polling Mailbox state in slaves

 

shall

3

CAN application layer over EtherCAT (CoE)

SDO Up/Download

Normal and expedited transfer

shall

Segmented Transfer

Segmented transfer

shall

4

Complete Access

Transfer the entire object (with all sub-indices) at once

shall

4

SDO Info service

Services to read object dictionary

shall

Emergency Message

Receive Emergency messages

shall

PDO in CoE

PDO services transmitted via CoE

may

EoE

EoE protocol

Services for tunneling Ethernet frames. includes all specified EoE services

shall

Virtual Switch

Virtual switch functionality

shall

EoE Endpoint to Operation Systems

Interface to the Operation System on top of the EoE layer

should

FoE

FoE Protocol

Support FoE Protocol

shall

Firmware Up-/Download

Password, FileName should be given by the application

shall

Boot State

Support Boot-State for Firmware Up/Download

shall

SoE

SoE Services

Support SoE Services

shall

AoE

AoE Protocol

Support AoE Protocol

should

VoE

VoE Protocol

External Connectivity supported

may

Synchronization with Distributed Clock (DC)

DC support

Support of Distributed Clock

shall

Continuous Propagation Delay compensation

Continuous Calculation of the propagation delay

should

5

Sync window monitoring

Continuous monitoring of the Synchronization difference in the slaves

should

5

Slave-to-Slave Communication

via Master

Information is given in ENI file or can be part of any other network configuration

Copying of the data can be handled by master stack or master’s application

shall

Master information

Master Object Dictionary

Support of Master Object Dictionary
(ETG.5001 MDP sub profile 1100)

should

1 called Process Data Domain within IgH EtherCAT Master®
2 APRW, FPRW, BRW not supported
3 basic support
4 only download supported
5 examples how to implement available

Table 2 EtherCAT Master classes (ETG.1500) features

Filling in the above table was challenging for the open source solutions as we had to search for all most all of the information in the source code itself. This is because documentation for what features are supported features is typically not available. IgH documentation is more complete than SOEM, however, the acontis documentation proved to be the best.

If the IRQ field in the EtherCAT datagrams is not checked, topology and slave state changes are not detected immediately. If your application contains e.g. tool changes this might be of concern for you.

Many slave manufacturers are defining mandatory CoE Init Commands (“InitCmds”) in the EtherCAT Slave Information (ESI) (EtherCAT Devices Description) file. This information is only available in the ESI file and can´t be read from the slave´s EEPROM as the EEPROM usually contains just default values. If the ESI files can’t be processed into an ENI and read-in by the stack these InitCmds must be implemented manually for those slaves to reach operational state (OP) → for each state change for every revision of that slaves. This can be tedious. Please refer to the appendix for further details.

As far as we could tell the two open source stacks have no ENI import capability nor slave-to-slave communication facilities, as a consequence they also do not support Safety over EtherCAT (FSoE = FailSafe over EtherCAT). If these are requirements or potentially future requirements for your project, you should reconsider using the open source stacks.

Problem

Short description

EC-Master

SOEM

IgH EtherCAT Master®

During network startup (typically unrecoverable error)

Master Configuration Missing

 

1

1

Bus mismatch - Line crossed

Support Slaves with and without application controller

1

Bus mismatch - Missing Slaves

Swap cables between IN and OUT port

1

1

Bus mismatch – Slave Swap

Not all configured slaves (as defined in the configuration file) could be found when scanning the actual connected bus

1

1

Cabling – Controller not connected to the network

The number of slaves is as configured, but the order is not the same

4

1

InitCmd error

Remove the bus cable from the Controller

1

2

Distributed Clocks synchronization issues

 

2

Permanent errors while network is operational

Slave switches to a lower state (SafeOp, PreOp, Init)

Slave will typically create an AL-Status IRQ and AL status error code

Master Controller - Cable disconnected

Disconnect the controller from the bus during operation

Master Controller - Cable reconnected

Reconnect the controller to the bus during operation

Network - Cable disconnected

Other cable disconnected or slave without power supply

Network - Cable reconnected

Plug-in cable or power-up slave

A Slave is faulty in a way, that no frame is responded to the master at all

ecatRescueScan(): Scans all connected slaves including closing ports

Intermittent errors/warnings

Frame loss

 

3

Working Counter Error (WKC) in cyclic data

 

5

Huge jitter for TX time

 

3

3

DC: DCM out-of-sync notification

 

2

1 Not “out of the box”, has to be programmed manually
2 No init commands supported
3 Very difficult to detect by design
4 No slaves found
5 Slave X lost

Table 3 Error handling

A detailed report about all these test cases and results can be obtained on request. As the table shows, error handling in IgH is slightly better than in SOEM. The biggest area where the open source stacks lack in error handling is during the startup of the network.

Conclusion

Depending on your platform (CPU, OS, network adapter, etc.) and other requirements there are many good solutions available. If you have a very static, small, and trivial network, the open source implementations might be a good choice. However, if your EtherCAT network configuration is prone to change and/or is very complex (e.g. contains drives, Modular Device Profiles (MDP)) or slaves with or without different HW/SW revisions where you have to adjust the default configuration (e.g. PDO mapping, Init commands) then you should select a stack that can import ENI files like the acontis EC-Master.

Appendix: Code Snippets to initialize a Yaskawa Sigma Drive

Open Source

Below you will find some SOEM test code to initialize the PDO Configuration of a Yaskawa Sigma Drive. In this case it is written on the state change from PreOp to SafeOP. Writing such a PDO configuration to the slave is similar with the IgH solution. All the indexes, sub-indexes and values have to be evaluated, copied and/or calculated and hard coded. Meta information like a comment for the single InitCmds is missing. Understanding what’s going on especially in the case of a misconfiguration or error is much harder. Working with ESI and ENI files is obvious more convenient. That’s what the EC-Master customers tell us. See also underneath the following listing.

static int YaskawaSigmaDrivePDOConfiguration (uint16 slave)
{
    int retval = 0;
    uint8 ui8Val = 0;
    uint16 ui16Val = 0;
    uint32 ui32Val = 0;
    ui8Val = 0;
    retval += ec_SDOwrite(slave, 0x1c12, 0x0, FALSE, sizeof(ui8Val), &ui8Val, EC_TIMEOUTSAFE);
    retval += ec_SDOwrite(slave, 0x1c13, 0x0, FALSE, sizeof(ui8Val), &ui8Val, EC_TIMEOUTSAFE);
    while(EcatError) printf("%s", ec_elist2string());

    ui8Val = 0;
    retval += ec_SDOwrite(slave, 0x1a00, 0x0, FALSE, sizeof(ui8Val), &ui8Val, EC_TIMEOUTSAFE);
    ui32Val = 0x60410010;
    retval += ec_SDOwrite(slave, 0x1a00, 0x1, FALSE, sizeof(ui32Val), &ui32Val, EC_TIMEOUTSAFE);
    ui32Val = 1617166368;
    retval += ec_SDOwrite(slave, 0x1a00, 0x2, FALSE, sizeof(ui32Val), &ui32Val, EC_TIMEOUTSAFE);
    ui32Val = 1618411536;
    retval += ec_SDOwrite(slave, 0x1a00, 0x3, FALSE, sizeof(ui32Val), &ui32Val, EC_TIMEOUTSAFE);
    ui32Val = 1626603552;
    retval += ec_SDOwrite(slave, 0x1a00, 0x4, FALSE, sizeof(ui32Val), &ui32Val, EC_TIMEOUTSAFE);
    ui32Val = 1616969736;
    retval += ec_SDOwrite(slave, 0x1a00, 0x5, FALSE, sizeof(ui32Val), &ui32Val, EC_TIMEOUTSAFE);
    ui32Val = 8;
    retval += ec_SDOwrite(slave, 0x1a00, 0x6, FALSE, sizeof(ui32Val), &ui32Val, EC_TIMEOUTSAFE);
    ui32Val = 1622736312;
    retval += ec_SDOwrite(slave, 0x1a00, 0x7, FALSE, sizeof(ui32Val), &ui32Val, EC_TIMEOUTSAFE);
    ui32Val = 1622802464;
    retval += ec_SDOwrite(slave, 0x1a00, 0x8, FALSE, sizeof(ui32Val), &ui32Val, EC_TIMEOUTSAFE);
    ui8Val = 8;
    retval += ec_SDOwrite(slave, 0x1a00, 0x0, FALSE, sizeof(ui8Val), &ui8Val, EC_TIMEOUTSAFE);
    while(EcatError) printf("%s", ec_elist2string());

    ui8Val = 0;
    retval += ec_SDOwrite(slave, 0x1a01, 0x0, FALSE, sizeof(ui8Val), &ui8Val, EC_TIMEOUTSAFE);
    ui32Val = 1614872592;
    retval += ec_SDOwrite(slave, 0x1a01, 0x1, FALSE, sizeof(ui32Val), &ui32Val, EC_TIMEOUTSAFE);
    ui32Val = 1617166368;
    retval += ec_SDOwrite(slave, 0x1a01, 0x2, FALSE, sizeof(ui32Val), &ui32Val, EC_TIMEOUTSAFE);
    ui8Val = 2;
    retval += ec_SDOwrite(slave, 0x1a01, 0x0, FALSE, sizeof(ui8Val), &ui8Val, EC_TIMEOUTSAFE);
    while(EcatError) printf("%s", ec_elist2string());

    ui8Val = 0;
    retval += ec_SDOwrite(slave, 0x1a02, 0x0, FALSE, sizeof(ui8Val), &ui8Val, EC_TIMEOUTSAFE);
    ui32Val = 1614872592;
    retval += ec_SDOwrite(slave, 0x1a02, 0x1, FALSE, sizeof(ui32Val), &ui32Val, EC_TIMEOUTSAFE);
    ui32Val = 1617166368;
    retval += ec_SDOwrite(slave, 0x1a02, 0x2, FALSE, sizeof(ui32Val), &ui32Val, EC_TIMEOUTSAFE);
    ui8Val = 2;
    retval += ec_SDOwrite(slave, 0x1a02, 0x0, FALSE, sizeof(ui8Val), &ui8Val, EC_TIMEOUTSAFE);
    while(EcatError) printf("%s", ec_elist2string());

    ui8Val = 0;
    retval += ec_SDOwrite(slave, 0x1a03, 0x0, FALSE, sizeof(ui8Val), &ui8Val, EC_TIMEOUTSAFE);
    ui32Val = 1614872592;
    retval += ec_SDOwrite(slave, 0x1a03, 0x1, FALSE, sizeof(ui32Val), &ui32Val, EC_TIMEOUTSAFE);
    ui32Val = 1617166368;
    retval += ec_SDOwrite(slave, 0x1a03, 0x2, FALSE, sizeof(ui32Val), &ui32Val, EC_TIMEOUTSAFE);
    ui32Val = 1618411536;
    retval += ec_SDOwrite(slave, 0x1a03, 0x3, FALSE, sizeof(ui32Val), &ui32Val, EC_TIMEOUTSAFE);
    ui8Val = 3;
    retval += ec_SDOwrite(slave, 0x1a03, 0x0, FALSE, sizeof(ui8Val), &ui8Val, EC_TIMEOUTSAFE);
    while(EcatError) printf("%s", ec_elist2string());

    ui8Val = 0;
    retval += ec_SDOwrite(slave, 0x1600, 0x0, FALSE, sizeof(ui8Val), &ui8Val, EC_TIMEOUTSAFE);
    ui32Val = 1614804056;
    retval += ec_SDOwrite(slave, 0x1600, 0x1, FALSE, sizeof(ui32Val), &ui32Val, EC_TIMEOUTSAFE);
    ui32Val = 1618608160;
    retval += ec_SDOwrite(slave, 0x1600, 0x2, FALSE, sizeof(ui32Val), &ui32Val, EC_TIMEOUTSAFE);
    ui32Val = 1627324448;
    retval += ec_SDOwrite(slave, 0x1600, 0x3, FALSE, sizeof(ui32Val), &ui32Val, EC_TIMEOUTSAFE);
    ui32Val = 1618018320;
    retval += ec_SDOwrite(slave, 0x1600, 0x4, FALSE, sizeof(ui32Val), &ui32Val, EC_TIMEOUTSAFE);
    ui32Val = 1618083856;
    retval += ec_SDOwrite(slave, 0x1600, 0x5, FALSE, sizeof(ui32Val), &ui32Val, EC_TIMEOUTSAFE);
    ui32Val = 1616904200;
    retval += ec_SDOwrite(slave, 0x1600, 0x6, FALSE, sizeof(ui32Val), &ui32Val, EC_TIMEOUTSAFE);
    ui32Val = 8;
    retval += ec_SDOwrite(slave, 0x1600, 0x7, FALSE, sizeof(ui32Val), &ui32Val, EC_TIMEOUTSAFE);
    ui32Val = 1622671376;
    retval += ec_SDOwrite(slave, 0x1600, 0x8, FALSE, sizeof(ui32Val), &ui32Val, EC_TIMEOUTSAFE);
    ui8Val = 8;
    retval += ec_SDOwrite(slave, 0x1600, 0x0, FALSE, sizeof(ui8Val), &ui8Val, EC_TIMEOUTSAFE);
    while(EcatError) printf("%s", ec_elist2string());

    ui8Val = 0;
    retval += ec_SDOwrite(slave, 0x1601, 0x0, FALSE, sizeof(ui8Val), &ui8Val, EC_TIMEOUTSAFE);
    ui32Val = 1614807056;
    retval += ec_SDOwrite(slave, 0x1601, 0x1, FALSE, sizeof(ui32Val), &ui32Val, EC_TIMEOUTSAFE);
    ui32Val = 1618608160;
    retval += ec_SDOwrite(slave, 0x1601, 0x2, FALSE, sizeof(ui32Val), &ui32Val, EC_TIMEOUTSAFE);
    ui8Val = 2;
    retval += ec_SDOwrite(slave, 0x1601, 0x0, FALSE, sizeof(ui8Val), &ui8Val, EC_TIMEOUTSAFE);
    while(EcatError) printf("%s", ec_elist2string());

    ui8Val = 0;
    retval += ec_SDOwrite(slave, 0x1602, 0x0, FALSE, sizeof(ui8Val), &ui8Val, EC_TIMEOUTSAFE);
    ui32Val = 1614807056;
    retval += ec_SDOwrite(slave, 0x1602, 0x1, FALSE, sizeof(ui32Val), &ui32Val, EC_TIMEOUTSAFE);
    ui32Val = 1627324448;
    retval += ec_SDOwrite(slave, 0x1602, 0x2, FALSE, sizeof(ui32Val), &ui32Val, EC_TIMEOUTSAFE);
    ui8Val = 2;
    retval += ec_SDOwrite(slave, 0x1602, 0x0, FALSE, sizeof(ui8Val), &ui8Val, EC_TIMEOUTSAFE);
    while(EcatError) printf("%s", ec_elist2string());

    ui8Val = 0;
    retval += ec_SDOwrite(slave, 0x1603, 0x0, FALSE, sizeof(ui8Val), &ui8Val, EC_TIMEOUTSAFE);
    ui32Val = 1614807056;
    retval += ec_SDOwrite(slave, 0x1603, 0x1, FALSE, sizeof(ui32Val), &ui32Val, EC_TIMEOUTSAFE);
    ui32Val = 1618018320;
    retval += ec_SDOwrite(slave, 0x1603, 0x2, FALSE, sizeof(ui32Val), &ui32Val, EC_TIMEOUTSAFE);
    ui8Val = 2;
    retval += ec_SDOwrite(slave, 0x1603, 0x0, FALSE, sizeof(ui8Val), &ui8Val, EC_TIMEOUTSAFE);
    while(EcatError) printf("%s", ec_elist2string());

    ui16Val = 5633;
    retval += ec_SDOwrite(slave, 0x1c12, 0x1, FALSE, sizeof(ui16Val), &ui16Val, EC_TIMEOUTSAFE);
    ui8Val = 1;
    retval += ec_SDOwrite(slave, 0x1c12, 0x0, FALSE, sizeof(ui8Val), &ui8Val, EC_TIMEOUTSAFE);
    while(EcatError) printf("%s", ec_elist2string());

    ui16Val = 6657;
    retval += ec_SDOwrite(slave, 0x1c13, 0x1, FALSE, sizeof(ui16Val), &ui16Val, EC_TIMEOUTSAFE);
    ui8Val = 1;
    retval += ec_SDOwrite(slave, 0x1c13, 0x0, FALSE, sizeof(ui8Val), &ui8Val, EC_TIMEOUTSAFE);
    while(EcatError) printf("%s", ec_elist2string());

    ui8Val = 8;
    retval += ec_SDOwrite(slave, 0x6060, 0x0, FALSE, sizeof(ui8Val), &ui8Val, EC_TIMEOUTSAFE);
    while(EcatError) printf("%s", ec_elist2string());

    printf("Servo slave %d set, retval = %d\n", slave, retval);
    return 1;
}

Snippet 1 Test code Yaskawa sigma drive initialization

EC-Master

As described before EtherCAT slave manufactures usually deliver an ESI file with their device. The collection of all the ESI files of your slaves describes your EtherCAT network. This file collection is usually processed –mostly with some graphical tool (e.g. EC-Engineer)– into an ENI. This ENI contains the whole network description. Besides a lot of other information also the commands (InitCmds) to be executed on every state change of every slave in every revision. The EC-Master reads in all this information. Whenever a slave state change is commanded to the EC-Master stack and from the stack to the slaves those state changed connected InitCmds are also send/commanded to the slaves. Imagining you have slaves in different revisions and have to change a PDO configuration with different initialization sequences with certain rule sets or attributes attached to it. Doing this on higher level safes both time and money. To initialize the EC-Master mainly the four bold functions listed below are need. The snippet initializes a whole multi-threaded EC-Master and the attached Network including Error-Handling, Logging and much more...

/* initialize EtherCAT master */
EC_T_INIT_MASTER_PARMS oInitParms;
OsMemset(&oInitParms, 0, sizeof(EC_T_INIT_MASTER_PARMS));
oInitParms.dwSignature                   = ATECAT_SIGNATURE;
oInitParms.dwSize                        = sizeof(EC_T_INIT_MASTER_PARMS);
oInitParms.pLinkParms                    = pAppParms->apLinkParms[0];
oInitParms.dwBusCycleTimeUsec            = pAppParms->dwBusCycleTimeUsec;
oInitParms.dwMaxAcycFramesQueued         = MASTER_CFG_MAX_ACYC_FRAMES_QUEUED;
OsMemcpy(&oInitParms.LogParms, &pAppContext->LogParms, sizeof(EC_T_LOG_PARMS));
oInitParms.LogParms.dwLogLevel = pAppParms->dwMasterLogLevel;
CHECK_MASTER_CALL( ecatInitMaster(&oInitParms), "Cannot initialize EC-Master: %s (0x%lx))\n" );

/* create cyclic task to trigger jobs */
CREATE_CYCLIC_TASK_TO_TRIGGER_JOBS

/* configure master */
CHECK_MASTER_CALL( ecatConfigureMaster(pAppParms->eCnfType,
                                       "YaskawaSigmaDrive.xml",
                                       (EC_T_DWORD)OsStrlen("YaskawaSigmaDrive.xml")),
                   "Cannot configure EC-Master: %s (0x%lx))\n" );

/* register client */
CHECK_MASTER_CALL( ecatRegisterClient(EcMasterNotifyCallback, pAppContext, &RegisterClientResults), "ERROR: Cannot register client: %s (0x%lx))\n" );
pAppContext->pNotificationHandler->SetClientID(RegisterClientResults.dwClntId);

/* state transition to OP */
CHECK_STATE_TRANSITION( ecatSetMasterState(ETHERCAT_STATE_CHANGE_TIMEOUT, eEcatState_INIT),   "INIT" );
CHECK_STATE_TRANSITION( ecatSetMasterState(ETHERCAT_STATE_CHANGE_TIMEOUT, eEcatState_PREOP),  "PREOP" );
CHECK_STATE_TRANSITION( ecatSetMasterState(ETHERCAT_STATE_CHANGE_TIMEOUT, eEcatState_SAFEOP), "SAFEOP" );
CHECK_STATE_TRANSITION( ecatSetMasterState(ETHERCAT_STATE_CHANGE_TIMEOUT, eEcatState_OP),     "OP" );

Snippet 2 EC-Master initialization