EC-Master V3.2: New Features

EC-Master V3.2.1 supports out-of-the-box the Texas Instruments TDA4VM Jacinto™ 7 processors.
For on-chip Ethernet controllers an dedicated high performance real-time Ethernet driver (Link Layer) is provided. The solution is available for the Linux operating system.
The implementation is already tested on the TI boards SK-TDA4VM, J721EXCPXEVM and J784s4.

EC-Master V3.2.1 supports out-of-the-box the NXP® i.MX 8 Series Applications Processors powered by QNX® SDP 8.0. For the implementation the Toradex Apalis iMX8 Computer on Module together with the Ixora Carrier Board was used. For on-chip Ethernet MACs the acontis Real-time Ethernet driver FSLFEC guarantees fast EtherCAT network update rates with low jitter.

The Beckhoff CU2508 real-time Ethernet port multiplier allows the connection of up to eight independent 100 Mbit EtherCAT network segments. The CU2508 is connected to the master controller via a Gigabit uplink (X9). The new acontis driver layer emllMultipler is responsible for routing the EtherCAT frames to the specific port.
Each network segment has its own configuration (ENI file). All segments can be operated by one single application process and may run with the same or different cycle times (update rates).
Precise synchronization based on Distributed Clocks (DC) is supported on all network segments. Each network has it's own reference clock.

The new version of EC-Master for Linux provides out-of-the-box support for several CPUs from the manufacturer Rockchip.
The acontis Real-time Ethernet Driver for Synopsys DesignWare® implements high-speed and low-jitter EtherCAT support for the on-chip Ethernet controller.
The following boards have been already successfully tested:

• Pine64 Rock64 with RK3328 (Quad Cortex A53)
• Orange Pi 4 with RK3399 (Dual Cortex-A72 + Quad Cortex-A53)
• Orange Pi 5 with RK3588s (Quad core Cortex-A76 + Quad-core Cortex-A55)
• Radxa Rock3 with RK3568 (Quad-Core ARM Cortex-A55)

The principles of synchronizing of an EtherCAT network with distributed clocks (DC) are explained on this page https://www.acontis.com/en/dcm.html
While the modes "DCM Master Shift“ and "DCM Bus Shift“ require a control loop running in the master to synchronize the EtherCAT system time with the master controller time, in the mode “DCM Master is Refclock” the system time is provided by the master itself. Therefore no DCM controller is required within the master. This saves CPU time and reduces complexity in the master implementation.
This System Time value (64-Bit) is distributed in every cycle frame with the command BWR to all slaves register 0x910. The time value itself is taken from a callback function which is registered with the API ecatDcmConfigure(). It's essential that the same time base is used for scheduling the cyclic JobTask and that the resolution is high enough.