EC-Master V3.2: New Features

EC-Master V3.2.2 supports out-of-the-box the powerful NVIDIA Jetson Orin™ embedded AI computers for generative AI, computer vision, and advanced robotics.

For on-chip Ethernet controller a dedicated high performance real-time Ethernet driver (Link Layer) is provided. The solution is available for the Linux operating system. The implementation is already tested on the NVIDIA Jetson Orin Nano Super Developer Kit.

EC-Master performance measurements on this platform have demonstrated very high CPU performance and excellent real-time capability. This allows even highly demanding EtherCAT applications with numerous SubDevices and a short cycle time of 250 us (4 kHz) to be implemented. The results are described in this blog.

EtherCAT Open mode is particularly useful when integrating EtherCAT networks into larger, shared IT environments. One or several EtherCAT segments may be connected to a standard (existing) switching device. Further information about EtherCAT Open Mode (EOM) is available in this blog.

In Open Mode, EtherCAT frames can be transmitted using either the communication type RAW or UDP. To reach the corresponding EtherCAT network segment in the frames, the destination MAC address must be set, and for UDP, also the destination IP address must be set.

Beside this, additional fields may need to be defined in the frame. These tasks are handled by the EOM Driver Layer, which is located above the acontis Real-time Ethernet drivers. The EOM Driver Layer can, of course, also operate multiple EtherCAT network segments. This means that only one physical Ethernet interface is required on the MainDevice.

In this approach, the EC-Master stack communicates with the SubDevices by sending and receiving EtherCAT frames via the Linux XDP kernel driver that controls the Ethernet network adapter (MAC).

The Linux kernel includes different network drivers for different adapter types. The Linux network driver can be used by means of an abstracted network adapter type independent interface called AF_XDP to send and receive frames. The XDP sockets interface has a better performance compared to the RAW sockets, but the Linux operating system must be designed for it and configured accordingly:

• The kernel must be at least V5.3 or newer
• The network driver must have XDP support (DRV mode) and be up-to-date
• CONFIG_XDP_SOCKETS must be enabled in the kernel configuration
• Required components: libxdp and libbpf

In this approach, the EC-Master stack communicates with the SubDevices by sending and receiving EtherCAT frames via the Data Plane Development Kit (DPDK) that controls the Ethernet network adapter (MAC). Data Plane Development Kit (DPDK) is a Linux Foundation project that consists of libraries to accelerate packet processing workloads running on a wide variety of CPU architectures.

The acontis real-time Ethernet driver emlldpdk uses DPDK libraries with an optimized packet processing path for fast transmission of EtherCAT frames. The library librte_eal provides the foundational API for DPDK, facilitating access to hardware resources such as memory, timers, and logs and is mainly used during initialization. The library librte_mbuf handles packet buffers that are crucial for packet transmission and reception. The library librte_ethdev offers an API for configuring and querying Ethernet devices. It supports various operations, including sending and receiving packets.

The system requirements and the kernel configuration for using DPDK on Linux are available here. The kernel must be at least V5.1 or newer.

DPDK does not use the standard Linux Ethernet drivers but provides its own drivers for a variety of different Ethernet controllers, including Intel Gigabit, NXP ENETFEC, etc. The complete list is available here.

Detailed instructions for using the real-time Ethernet driver emlldpdk can be found in the user documentation.

EC-Master V3.2.1 supports out-of-the-box the Texas Instruments TDA4VM Jacinto™ 7 processors.

For on-chip Ethernet controllers an dedicated high performance real-time Ethernet driver (Link Layer) is provided. The solution is available for the Linux operating system.

The implementation is already tested on the TI boards SK-TDA4VM, J721EXCPXEVM and J784s4.

EC-Master V3.2.1 supports out-of-the-box the NXP® i.MX 8 Series Applications Processors powered by QNX® SDP 8.0. For the implementation the Toradex Apalis iMX8 Computer on Module together with the Ixora Carrier Board was used.

For chip Ethernet MACs the acontis Real-time Ethernet driver FSLFEC guarantees fast EtherCAT network update rates with low jitter.

The Beckhoff CU2508 real-time Ethernet port multiplier allows the connection of up to eight independent 100 Mbit EtherCAT network segments. The CU2508 is connected to the master controller via a Gigabit uplink (X9). The new acontis driver layer emllMultipler is responsible for routing the EtherCAT frames to the specific port.
Each network segment has its own configuration (ENI file). All segments can be operated by one single application process and may run with the same or different cycle times (update rates).
Precise synchronization based on Distributed Clocks (DC) is supported on all network segments. Each network has it's own reference clock.

The new version of EC-Master for Linux provides out-of-the-box support for several CPUs from the manufacturer Rockchip.
The acontis Real-time Ethernet Driver for Synopsys DesignWare® implements high-speed and low-jitter EtherCAT support for the on-chip Ethernet controller.
The following boards have been already successfully tested:

• Pine64 Rock64 with RK3328 (Quad Cortex A53)
• Orange Pi 4 with RK3399 (Dual Cortex-A72 + Quad Cortex-A53)
• Orange Pi 5 with RK3588s (Quad core Cortex-A76 + Quad-core Cortex-A55)
• Radxa Rock3 with RK3568 (Quad-Core ARM Cortex-A55)

The principles of synchronizing of an EtherCAT network with distributed clocks (DC) are explained on this page https://www.acontis.com/en/dcm.html
While the modes "DCM Master Shift“ and "DCM Bus Shift“ require a control loop running in the master to synchronize the EtherCAT system time with the master controller time, in the mode “DCM Master is Refclock” the system time is provided by the master itself. Therefore no DCM controller is required within the master. This saves CPU time and reduces complexity in the master implementation.
This System Time value (64-Bit) is distributed in every cycle frame with the command BWR to all slaves register 0x910. The time value itself is taken from a callback function which is registered with the API ecatDcmConfigure(). It's essential that the same time base is used for scheduling the cyclic JobTask and that the resolution is high enough.